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SubjectRe: [OFFTOPIC] UltraSparc MMU problems
   Date: Tue, 27 Oct 1998 21:35:16 +1100
From: Richard Gooch <>

David S. Miller writes:
> Solaris's TLB miss strategy is pretty hopeless...

What does the OS have to do with it? Once the TLB's are set up, why
does the OS need to intervene?

If the OS uses a stupid scheme to replace a missing TLB entry and uses
inefficient tables as backing store for mappings, it will thrash the
L2 cache.

Note that Solaris and some other svr4 folks swap page tables out to
disk when memory is tight... when they get tapped back in you might
not get the nice cache patterns you had before...

BTW: we have FORE systems ATM cards in these machines, so that
probably rules out Linux anyway :-(

We have half-way done drivers for those, but there is still a lot of
work to do. Actually if I remember correctly, these cards are very
similar to the one's Werner Almesberger wrote drivers for in the
Linux/ATM project. His were PCI but the chipsets are the same as the
SBUS ones on Sparc systems.

David S. Miller

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