Messages in this thread | | | Date | Tue, 30 Sep 1997 16:13:03 -0400 | From | mlord <> | Subject | Re: Bus-Mastered DMA support for Triton Chipset? |
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Richard S. Gray wrote: ... > going on. I first compile support into my kernel by selecting: > > [*] Intel PIIX/PIIX3/PIIX4 (Triton 430FX/HX/VX/TX, 440FX) DMA support > > I then added the following code to my rc.local initialization script: ... > echo "Setting hda transfer mode to DMA mode2" > /sbin/hdparm -d1 -X34 /dev/hda > echo "Setting hdb transfer mode to DMA mode2" > /sbin/hdparm -d1 -X34 /dev/hdb ... > However, when cat /proc/dma I get: > > 1: SoundBlaster8 > 4: cascade > 5: SoundBlaster16 > > I believe the DMA BusMastering is probably working but I would like to > understand a little more about > what is going on. Shouldn't a channel be allocated for the ide drive? > Or does this form of DMA bypass > the DMA controller found on the main board. If yes then does this mean > that the DMA controller is > actually on the drive itself?
The PIIX chip (part of the "triton" chipsets) includes a dedicated DMA controller for each IDE interface. That's why no allocation is required as would be shown in /proc/dma.
-ml
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