Messages in this thread | | | Date | Tue, 22 Jul 1997 10:53:49 -0500 (CDT) | From | "Patrick St. Jean" <> | Subject | Re: question about M2 "feature" |
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Ok... here's the dirt straight out of Cyrix's databook:
Page 1-1: To provide for multimedia operations, the cache can be turned into a scratchpad RAM memory on a line by line basis. The cache area set aside as scratchpad memory acts as a private memory area for the CPU and does not participate in cache operations.
Page 1-16: The 6x86MX CPU has the capability to "lock down" lines in the L1 cache on a line by line basis. Locked down lines are treated as private memory for use by the CPU. Locked down memory does not participate in hardware cache coherency protocols. Cache locking is controlled through the use of the RDMSR and WRMSR instructions.
Page 2-61 (too long... I'm not typing this one...)
Here's the URL to get the databooks: http://www.cyrix.com/process/hardwrdc/6xmx-dbk.htm
Hope this helps...
Pat
-- +-----------------------------------------------------------------------------+ | Patrick St. Jean psj@cgmlarson.com | | Programmer & Systems Administrator +1 713-977-4177 x106 | | Larson Software Technology http://www.cgmlarson.com | +-----------------------------------------------------------------------------+
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