Messages in this thread |  | | | Date | Tue, 17 Jun 1997 10:16:03 -0400 | | From | mlord <> | | Subject | Re: TritonII IDE interface not PCI compliant? |
| |
Richard B. Johnson wrote: > > On Mon, 16 Jun 1997, Rogier Wolff wrote: > > > If my preliminary tests are correct, the IDE interface from the > > Triton/Natoma chipset, the 82371SB chip, is not using the "Latency" > > counter. ... > > This is my IDE interface according to /proc/pci: > > > > Bus 0, device 1, function 1: > > IDE interface: Intel 82371SB Natoma/Triton II PIIX3 (rev 0). > > Medium devsel. Fast back-to-back capable. Master Capable. > > Latency=32. I/O at 0xe800. > > > > Whenever I do disk access (dd if=/dev/hda of=/dev/null works nicely), > > I get tons of overruns from the other board. > > > > To me this indicates that the 82371SB isn't honoring the latency > > counter. Anybody have a different explanation? Anybody see the same? .. > The real fix is probably DMA (hense SCSI). > > I don't think the IDE interface is capable of DMA.
The IDE interface is already using full scatter-gather bus-master DMA (considerably faster than all but the highest-end SCSI interfaces), which is the whole point of this discussion about the PCI latency timers..
In this case, the other data-capture PCI device is likely the source of trouble (no guarantee though, as Intel ain't exactly forthcoming in letting anyone know about bugs in *their* chips); investigations are ongoing.
-ml
|  |