Messages in this thread | | | Date | Thu, 12 Jun 1997 12:23:24 +0100 (GMT/BST) | From | Mike Jagdis <> | Subject | Re: Saving syscall cycles on a Cyrix |
| |
On Thu, 12 Jun 1997, Thomas Koenig wrote:
> prompted by a discussion on comp.sys.development.system, I had a look > at entry.S, and found that this can be speeded up significantly for > a Cyrix. > > The problem is that two pushl/popl instructions can't be paired in the > Cyrix' X and Y pipelines because the esp register gets modified > in both. > > [...] > > only takes four, because any two instructions can pair. The same > goes for the reverse, i.e. the popl instructions. Cyrix patch > maintainers, are you listening? :-)
Most modern x86 processors have dual pipelines and can benefit from similar optimizations. The current gcc isn't particularly smart about interleaving code paths to avoid "bubbling" in the pipelines. I've been reading up on such tuning recently and, if anyone is interested, have hand tuned the rc5 cracking code to go from ~145K keys/s (on my machine) to ~205K keys/s (yes, you can get a big difference!). Of course, this is at the assembler level and the result is, ah, "not easily readable" but even paying attention to the order you do things in C can show reasonable gains. Whether such things are good for MIPS, Sparc, Alpha, PPC etc. as well is another question :-).
Mike
-- .----------------------------------------------------------------------. | Mike Jagdis | Internet: mailto:mike@roan.co.uk | | Roan Technology Ltd. | | | 54A Peach Street, Wokingham | Telephone: +44 118 989 0403 | | RG40 1XG, ENGLAND | Fax: +44 118 989 1195 | `----------------------------------------------------------------------'
| |