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SubjectRe: ISA bus and SLOW_DOWN_IO

Just my 2 Pesetas (about 1.4 cents), to the bunch if messages on the subject:

> Port addresses above 0xffff
> appear ONLY on the PCI bus. This allows one to use port I/O and still
> keep the high-speed signals off the ISA bus.

it is impossible to generate I/O address above 0xFFFF on an x86 processor
(well the 450[GK]X doc states it is possible in real mode but I don't know
how). PCI itself is not limited, and indeed on my PPC board the Ethernet
interface (DEC21140, driver de4x5) lives happily at 0x1000100 (I think this
is because of a PCI setup bug in the firmware but it doesn't matter).
On most systems, when the processor to PCI bridges starts an I/O cycle
(most likely as a result of an in or out instruction from the processor),
there are three possibilities:

1) a PCI device recognizes the address (asserts DEVSEL) and the cycle
proceeds,

2) the PCI to ISA bridge recognizes the address as one of its internal
registers, it asserts DEVSEL, and the cycle proceeds,

3) after a given number of PCI clock cycles, no PCI device responds, then
the PCI to ISA bridge claims the cycle (asserts DEVSEL) and translates it
into an ISA cycle, this is called "subtractive decoding".

BTW: many ISA boards only decode the ten lower address bits on the bus,
which means that they are aliased every 0x400. This is often a problem
and that's the reason for some weird tricks. All addresses between 0x100 and
0x3ff are potentially aliased which means that 3/4 of the I/O space
are unusable.

On Mon, 26 May 1997 Eric.Schenk@dna.lth.se wrote:

> But we should be able to use the same principle. On at 33Mhz 486 we
> get about 20 clock ticks in 600ns. When we are talking a 200Mhz Pentium
> we are looking at 120 clock ticks. We should be able to calabrate a small
> bit of loop code so that it takes about 600ns on pretty much anything
> that will run Linux. Say use a 16Mhz 386 as the worst case. I assume
> that even that slow a processor can make it once around a countdown loop
> in 10 clock ticks.
>
> (Or did one of slip a decimal somewhere here?)

No, it seems about right. If your loop is something like:
mov magic_constant,%eax
1: dec %eax
jnz 1b
with magic_constant set to one it should be 500 to 600 ns on a 16 MHz 386,
if I've got the timings right. But I still think that port 0x80 is quite
safe, however a write may not be the best solution since it can be posted
while a read returns a value only after it has completed on the whole bus
hierarchy. According to the chipset documentations I have seen, I/O space
accesses are never posted however. Why not a read on a port which is known
to be free from side effects ?

BTW: for people having a PIIX/PIIX3 PCI to ISA bridges, it is possible to
program them for fairly large I/O recovery times between cycles on the ISA
bus (up pto 1 microsecond). This should be a BIOS option setting but not
all BIOSes implement it of course :-(

Gabriel.




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