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SubjectRe: ISA bus and SLOW_DOWN_IO
On Sun, 25 May 1997 Eric.Schenk@dna.lth.se wrote:

>
> "Richard B. Johnson" <root@analogic.com> writes:
> >Now, using the "old fashoned" pause method of:
> >
> > jmp foo
> > foo:
> >
> >Is not too effective because with high-speed CPUs and built-in caches,
> >you will not waste enough time. However, accessing RAM is predictable
> >because PC class RAM access times will not get much faster than 60 ns.
> >
> >I suggest that the macro be changed to:
> >
> > pusha
> > popa
> >
> >This will access the stack with a known number of processor clocks plus
> >read/write access time. These accesses are not on the ISA bus.
>
> Ok, I follow everything up to this point, and it all makes perfect
> sense to me, but wont the above delay with memory accesses usually
> end up in the L1 cache or L2 cache? In which case we're back to the
> clock speed of the processor, or at least near to it.
>
> I suggest that this is a place where we need to make
> use of our carefully calculated BOGOMIPS number. If someone can look up
> exactly how long a delay we want here, we can calabrate a loop that
> takes the right amount of time.

The problem is that we need 300 to 600 ns! BogoMips isn't going to do it.
It is true that we are back to the clock-speeds of the uP, but the RAM
stack access times dominate. Anything greater than 600 nanoseconds wastes
time. Anything less than 300 may result in the glitches. This does not
have to be very accurate.


Cheers,
Dick Johnson
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Richard B. Johnson
Project Engineer
Analogic Corporation
Voice : (508) 977-3000 ext. 3754
Fax : (508) 532-6097
Modem : (508) 977-6870
Ftp : ftp@boneserver.analogic.com
Email : rjohnson@analogic.com, johnson@analogic.com
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