Messages in this thread | | | Date | Thu, 25 Dec 1997 17:11:00 +0100 (MET) | From | Gerard Roudier <> | Subject | Re: Race conditions galore (2.0.33 and possibly 2.1.x) |
| |
On Thu, 25 Dec 1997, Alan Cox wrote:
> > >Misused or mishandled 'PCI write and invalidate' commands may > > >cause cache coherency problems. If the 53C875 is using this > > >feature, I would suggest to disable it. > > > > Well, it is very unlikely that the problem is a direct result > > of failed SCSI-bus-mastering. The problem seems to occur *before* > > the disk activity takes place. > > The NCR controllers do bus mastering cycles - including several that catch > out crap chipsets _before_ they touch disks - the scripts that the controller > runs are fetched for its processor this way.
Earliest NCR8XX (810) chips did a bus mastering cycle for each DWORD script instruction.
The SYM53C875 is able to prefetch 8 DWORDs in a single PCI transaction for SCRIPTS executed out of main memory. On the other hand, it offers 4K bytes (1K DWORDS) of on-chip RAM for SCRIPTS instructions, and since ncr53c8xx driver version 1.18b (27 feb 1997), the most frequently (normal cases) used SCRIPTS are loaded into the on-chip RAM. When the 875 fetches SCRIPTS instructions from its on-chip RAM, no PCI transaction will take place. These features allows to dramatically decrease the PCI activity needed by the controller to execute SCSI SCRIPTS.
Regards, Gerard.
| |