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SubjectRe: Race conditions galore (2.0.33 and possibly 2.1.x)
Date
> >Misused or mishandled 'PCI write and invalidate' commands may 
> >cause cache coherency problems. If the 53C875 is using this
> >feature, I would suggest to disable it.
>
> Well, it is very unlikely that the problem is a direct result
> of failed SCSI-bus-mastering. The problem seems to occur *before*
> the disk activity takes place.

The NCR controllers do bus mastering cycles - including several that catch
out crap chipsets _before_ they touch disks - the scripts that the controller
runs are fetched for its processor this way.

Alan


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