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SubjectRe: linux/merced
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> I hate to bring this up again, just when this thread had died...
...
> Compiler questions, for those that know: How flexible is the gcc backend?
> Is the machine-description language used by gcc able to describe something
> like merced?

"Divide and concure" -- VLIW machines can be considered as
super-scalar processors with parallellism visible to outside.
(So now it is not any mythical monster, I hope.)

The GCC can handle several super-scalar topics quite well
already (since 2.6.0, I think), and the only thing you really
would need is to write a machine descriptor for it.

Writing the machine descriptor -- now that is a challenge
to do in order to get the performance out of the processor.
(Things like dataregister access latensies from previous
instruction storing there something to when next instruction
can read the same register, etc. "trivia"..)

SuperSPARC optimization in GCC is rather good, while the latter
models of Alpha are somewhat lacking as of 2.7.2.x ...

Anyway, I recall i860 processor was successfully implemented
in GCC, and in that processor the pipelines are VERY VISIBLE.
Even so much so, that if you multiply something, you must have
4 multiplication instructions in sequence in order to get result
out from the multiplier. (One with datas, and three with dummies.)
Of course rarely repeating multiplications in such a machine
are not very efficient, but on the other hand, large number of
multiplications can be piped quite efficiently with minimum
(= none) dummy cycles.

> Advice, guidance, enthusiasm and/or discouragement welcome.
> --Scott
> C. Scott Ananian: cananian@lcs.mit.edu / Declare the Truth boldly and

/Matti Aarnio <matti.aarnio@tele.fi>

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