Messages in this thread | | | From | "Ulrich Windl" <> | Date | Wed, 17 Apr 1996 08:38:45 +0100 | Subject | Re: Cache Control |
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On 16 Apr 96 at 2:56, Howard C. Tyler wrote:
> > My bios (AMI rev.F for MTI-r407e mb) has bugs affecting > both on-chip (L1) and off-chip(L2) caches. Not only does this > bios not enable the dirty-tag bit in the L2 cache, but if the > "bios setup" is configured for "L1 write-back" and "L1-disabled", > the L1 cache is NOT disabled. > Write-back cache requires hardware support. The AMD > "Enhanced 486" and "586" cpus select either write-back or > write-thru mode after reset by the voltage on pin B13. If the > cpu is wired for write-back, but the bios does not or can not > configure the motherboard to support the L1 write-back cache, > caching inconsistencies will arise. That is, what the cpu thinks > it wrote to memory may not be what another bus-mastering device > finds in ram. > Even if bios gets it right, Linux does not honor the bios's > configuration. Linux always enables the L1 cache by zeroing the > CD bit in cr0. Linux also zeros the NW bit in cr0. If the L1 > cache is to be disabled, both these bits should be 1. > Attached is a patch, against 1.3.86, that leaves CD and > NW bits they way bios set them. The patch also enhances the > right-ctl+srool-lock display to show the value of cr0. If cr0 > is 0x8xxx xxxx, L1 caching is enabled, if cr0 is 0xExxx xxxx, > L1 is disabled. > I suspect that caching and the newer 486 cpu's are the > source of some of the strange OOPS's. YMMV ;-)
Good work! What about "yais" (yet another init string) like "cpuflags=", or "cachecontrol="?
> > Howard > > ---- Cut Here ------- OK!
Ulrich
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