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    SubjectRe: What happened to the 4MB paging Pentium bug?

    At 23:11 27.11.1996 +0000, Alan Cox wrote:
    > Does anyone know how the B1,B3,B5 .. map to the version info
    > in CPUID ??

    At 15:22 27.11.1996 -0500, Andrew E. Mileski wrote:
    >Version levels for the CPU.
    >
    >Note: My Pentium-166 has a stepping level of 12.


    1. This should be fixed in /proc/cpuinfo:
    stepping levels 10, 11, 12 should be written
    as A, B and C (see Intel documentation).

    2. There exist (I hope I've got them all looking through
    the tables) steppings (CPUID) 0-7 and A-C.

    3. Intel differentiates between steppings reported by CPUID
    and "Manufacturing Steppings":

    stepping man. stepping
    -------------------------------------------------------------
    0 mA4 (75+ MHz (model = 7 ?!?!?! - should be 2))
    1 B1
    2 B3
    3 B1 (60/66 MHz only => model = 1)
    4 B5
    5 C1 (60/66 ...)
    5 C2, mA1
    6 E0
    7 D1 (60/66 ...)

    A tA0 (Overdrive 120/60, 133/66, model =1)
    B cB1, mcB1
    C cC0, mcC0

    m - prefix means mobile (Voltage Reduction Technology, 3.3 V etc.)

    Intel also says:
    "The cB1 stepping is logically equivalent to the C2-step, but on a different
    manufacturing process. The mcB1 step is logically equivalent to the cB1
    step ..."

    This means stepping B (=11) processors should have the same problems like
    the 5th stepping CPU's. BUT I couldn't find anything about a 4MB paging bug
    with
    these steppings except for a "specification clarification" which states, that
    after setting the CR4 PSE bit the TLB should be flushed by writing to CR3.

    ...

    CONFUSED? -- read the full documentation's text at

    http://www.intel.com/design/pentium/update/DWNLOD.HTM



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